The absorption length of 850 nm light in silicon is 15-20 microns, which is much longer than the 1-2 microns absorption length of typical III-V compound semiconductors such as GaAs at this wavelength. As a result, high speed silicon photodetectors are often designed with a lateral structure, rather than a vertical structure, in an attempt to decouple the photocarrier transient time from the absorption length and to minimize the complexity of fabricating large scale features, since semiconductor processing is typically optimized for thin film (<<1 μm) features.
These lateral structures typically take the form of either (1) a p-i-n detector with diffused or implanted fingers, or (2) a metal-semiconductor-metal (MSM) detector. In such lateral structures, the electric field is high at the surface of the semiconductor and decreases at lower depths. Photocarriers that are generated deep below the surface of the semiconductor experience a weak electric field and slowly drift up to the contacts. These slow carriers create a low frequency tail in the frequency response that limits the bandwidth of the device to be less than 1 GHz in silicon. This effect can somewhat be minimized by using a lateral trench detector (LTD) structure.
U.S. Pat. No. 6,177,289 to Crow et al. provides one such LTD structure. The LTD structure is formed within a plurality of substantially parallel trenches that are etched into a substrate. The trenches are further formed as a plurality of alternating n-type and p-type trench regions separated by pillar regions of the substrate which operate as an intrinsic (i) region between the n and p trench regions. First and second contacts are formed on the surface of the substrate and interconnect the n-type trench regions and the p-type trench regions, respectively. Preferably, the trenches are etched with a depth comparable to an optical extinction length of optical radiation to which the detector is responsive.
U.S. Pat. No. 6,451,702 to Yang et al. provides another LTD structure. In particular, Yang et al. provides a method of forming a LTD structure which includes forming a first set and a second set of trenches in a substrate, wherein trenches of the first set are alternately disposed with respect to trenches of the second set, filling the trenches with a sacrificial material, and etching the sacrificial material from the first set of trenches. The method further includes filling the first set of trenches with a doped material of a first conductivity, etching the sacrificial material from a second set of trenches, filling the second set of trenches with a doped material of a second conductivity, forming a first junction layer by driving dopants from the doped material in each of the first set of trenches and forming a second junction layer by driving dopants from the doped material in each of the second set of trenches, and providing separate wiring connections to the first set of trenches and the second set of trenches. The first and second sets of trenches are formed simultaneously.
The prior art LTD structures such as described, for example, in Crow et al. and Yang et al. are based on DRAM (dynamic random access memory) capacitor trenches that are filled with p-type and n-type polysilicon to form a lateral p-i-n structure. The trenches are typically formed by reactive ion etching (RIE). Typical trenches can be 100 nm wide and about 8 microns deep. Since n-type and p-type filled trenches are needed to realize the p-i-n structure, the fabrication process typically requires two RIB steps. Alternatively, all trenches are etched in one RIE step and then filled with a sacrificial material. The sacrificial material is removed from designated p-type trenches to allow p-type filling of the trenches and then the sacrificial material is removed from designated n-type trenches and thereafter filled with a p-type material. Each polysilicon deposition step is typically followed by a chemical mechanical polishing (CMP) step to remove the excess polysilicon from the device top surface.
The LTD structure fabrication requires specialized silicon technology processes, such as high aspect ratio reactive ion etching, in-situ doped polysilicon deposition, and multiple CMP steps. Also, it is more difficult to integrate trenches with semiconductor-on-insulator (SOI) technology due to the presence of the buried insulating layer. Additionally, and on one hand, since the RIE process can produce trenches with finite aspect ratio of depth over width, reducing the trench width will result in shallower trenches and therefore loss of detector responsivity. On another hand, wide trenches reduce the intrinsic silicon available for carrier absorption.
In view of the above, there is a need for providing a new p-i-n structure which is based on the same operation principle used by LTD structures, yet avoids the problems and fabrication complexity of LTD structures.